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thomasmathew · 12-17-2003, 01:52 PM

Hai linux gurus,
I am newbie to this linux programming and I so craze of masterising it. I am having a doubt about what is the difference between a shell script and a makefile specifications? Is it the same way makefiles and shell scripts are writing?

please forgive me if absurd. Also I want to what is meant by a spec file and what is its use? Can anybody suggest a text or online resource to masterise linux programming? Thank you to all the guys who respond to me. Thirst of

linux programming....

acid_kewpie · 12-17-2003, 03:16 PM

a shell script is an abritrary collection of unix shell commands. put a command in a file and it is a shell script. a Makefile however is a very clever bit of scripting (in it's own language to all extents) that compiles an accompanying set of source code into a program. a spec file is typically a definition of an RPM file, what certain commands are required to run it, what it requires to work correctly and such.

dolmen · 12-17-2003, 05:52 PM

The content of a Makefile is evaluated by the 'make' program.
The content of a shell script is evaluated by the shell program (usually bash on GNU systems).

What may be confusing you is that both contains call to other programs. In fact make use the shell to execute some commands in the makefile (lines that begins with a tab) based on modification time of files.

thomasmathew · 12-18-2003, 11:45 AM

Thank You to everybody for there valuable reply. Now how can I write a make file. I am interested in knowing more tutorials and resources for creating error free make files. want to

more details about make files.

Help Me dear

dolmen · 12-18-2003, 05:11 PM

I did a search on Google with the words "Make" and "tutorial".
http://www.google.fr/search?q=Make+t...e+Google&meta=

The first link seems to be what your are looking for:
http://www.eng.hawaii.edu/Tutor/Make/

vasudevadas · 12-19-2003, 04:35 AM

If you're writing a program called my_prog, with two source files my_prog.c and my_prog.h, you can say: my_prog depends on my_prog.c and my_prog.h, that is to say; if either my_prog.c or my_prog.h are changed, my_prog must be recompiled. You put this information into a makefile like this:

Code:

my_prog: my_prog.c my_prog.h
        gcc -o my_prog my_prog.c

The first line tells make what the dependencies of my_prog are. The general form is:

Code:

<target>: <dependencies>

As you can see, the various dependencies are listed separated by spaces.

The second line tells make what command to execute if my_prog needs to be recompiled, i.e. if either (or both) of my_prog.c and my_prog.h have changed since my_prog was last compiled. As you can see, in this case the command is an invokation of the C compiler. Command lines must always begin with a tab character.

This is a fairly trivial example, because we only have one source .c file. Makefiles come into their own where a project has multiple sources:

Code:

my_prog: my_prog_1.o my_prog2.o
        gcc -o my_prog my_prog_1.o my_prog_2.o

my_prog_1.o: my_prog_1.c my_prog.h
        gcc -c my_prog_1.c

my_prog_2.o: my_prog_2.c my_prog.h
        gcc -c my_prog_2.c

Much more can be said about makefiles, but this is the basics.

thomasmathew · 12-19-2003, 11:27 AM

Hai Thank You for your information. But I have seen a couple of makefiles that is having some $ such as some menmonics like $^, $@ etc after the tab. I do not know how to interpret it into valid linux commands. Please give me the assistance to grasp what these lines represent.

I have also seen lines like

clean:
rm -f *.o *- core

These lines are so

!!!! Please gimme the details of these mnemonics so as to avoid the

Thank You to all the Penguin freaks for the guidance.

to hear from you.

vasudevadas · 12-19-2003, 12:38 PM

What I told you above was the absolute basics. Makefiles get much more complicated, as you are seeing.

You can put macros in makefiles, these are what the dollar signs mean. A usual example is to use a macro for the command that invokes your compiler:

Code:

CC = gcc

my_prog: my_prog.c my_prog.h
        $(CC) -o my_prog my_prog.c

This is because the command to invoke the compiler varies from machine to machine. On Linux it is usually gcc, but on a Unix system it will probably be cc. If you use a macro for it then you only have to change it in one place - where the macro is defined - in order to make the makefile work on another system.

Macros are commonly used to save typing too, like using one for the flags you pass to the compiler:

Code:

CC = gcc
CFLAGS = -o

my_prog: my_prog.c my_prog.h
        $(CC) $(CFLAGS) my_prog my_prog.c

There's no point to it in the above example, but if you are writing a big makefile with lots of commands, and passing lots of flags to the compiler then you can see the effort saved.

An at (@) symbol at the beginning of a command line means that the command being executed will not be echoed to the screen. Think of it like a "silent" option. I have no idea what circumflex (^) symbols mean, you will have to look that up in a reference somewhere.

As for bits like:

Code:

clean:
	rm -f *.o *.-core

To understand this, you need to know that you can pass arguments to the make command. Simply issuing make with no arguments causes the make utility to look for a makefile called "makefile" or "Makefile" and updates every target contained therein that requires updating. If you issue the command:

Code:

make <target>

then make will only update the named target within the makefile. So if you have a target "clean" defined in your makefile as in the example above, issuing the command

Code:

make clean

will cause the make utility to issue the command:

Code:

rm -rf *.o *-core

i.e. remove all files in the current directory and all subdirectories that have filenames ending in .o and .core. This is a "clean up" hence the target name "clean". You will probably also see targets defined called "install" that copy executable files to places like /usr/local/bin, the effect of issuing "make install" after a "make" is thus to copy the newly compiled executables into the relevant place so that it can be accessed just like any other system command. You should notice that in these examples, the target does not actually refer to a file that gets created. It doesn't have to. Clever, eh?

If you have understood all this so far then you should look for more information in various references, the O'Reilly book "Unix in a Nutshell" has a good section on the make utility. I have run out of knowledge I can give you, I hope it helped.

thomasmathew · 12-20-2003, 12:59 PM

Thanks a lot for your interest in taking time and replying to me.

I came up with writing the make files when I read the book of Linux Device Drivers - O'Reilly Publications. There is a make file written for compiling and linking two source files in the second chapter for a sample program called 'skull'. May I put the make file as written in the book.

__________________________________________________________

# Change it here on specify it on the 'make' command line.
KERNELDIR= /usr/src/linux

include $(KERNELDIR)/.config

CFLAGS= -D__KERNEL__ -DMODULE -I$(KERNELDIR)/include \
-O -Wall

ifdef CONFIG_SMP
CFLAGS += -D__SMP__ -DSMP
endif

all:skull.o

skull.o: skull_init.o skull_clean.o
$(LD) -r $^ -o $@

clean:
rm -f *.o *~ core

__________________________________________________________

Can you please explain these lines to what it mean?

Here you can clearly see the usage of $^ and $@ representing some mnemonics for the linking.

What is the use of the including the file .config?

Besides, why the SMP is defined twice like -D__SMP__ aswell as -DSMP? Is it this an OR condition for the programs that uses the __SMP__ or the SMP as the compiler control variables?

Also what is the meaning of the CFLAGS option flag macro assignment line.

Also *.o is an object file. But what is that filed formed during compilation called the *~ core

As a fact I just want to know meaning for the full lines of code above dear

Please teach me!!!!! Hoping to seek a vauable reply.

dolmen · 12-22-2003, 05:15 PM

$^ is the list of input files (skull_init.o, skull_clean.o).
$@ is the target file (skull.o)

The clean target is usually used to removed unneeded files.
*~ are backup files created by some text editors.
core is a file created by the kernel when a program crashes (which can happen during the development).

thomasmathew · 12-23-2003, 12:00 PM

May I first of all express my

to you all for the guidance support.

Can anybody tell about more such $ mnemonics like the $^ and $@? What is the name given to this type of mnemonics in the linux jargon?

Please list the set of such $ prefix in the creation of a typical makefile.

with

Thomas.

vasudevadas · 12-23-2003, 03:08 PM

Like dolmen said, $@ is the target file, so you could say:

Code:

my_prog: my_prog.c my_prog.h
	gcc -o $@ -c my_prog.c

I'm afraid I have no idea what the special macro $^ does. Type "makefile" into google and you will find a great deal of information.

12-17-2003, 01:52 PM	#1
thomasmathew LQ Newbie Registered: Apr 2003 Location: India Distribution: Red Hat 8.0 Posts: 23 Rep:	Shell Script and makefile [Log in to get rid of this advertisement] Hai linux gurus, I am newbie to this linux programming and I so craze of masterising it. I am having a doubt about what is the difference between a shell script and a makefile specifications? Is it the same way makefiles and shell scripts are writing? please forgive me if absurd. Also I want to what is meant by a spec file and what is its use? Can anybody suggest a text or online resource to masterise linux programming? Thank you to all the guys who respond to me. Thirst of linux programming....

12-19-2003, 04:35 AM	#6
vasudevadas Member Registered: Jul 2003 Location: Bedford, UK Distribution: Slackware 11.0, LFS 6.1 Posts: 519 Rep:	If you're writing a program called my_prog, with two source files my_prog.c and my_prog.h, you can say: my_prog depends on my_prog.c and my_prog.h, that is to say; if either my_prog.c or my_prog.h are changed, my_prog must be recompiled. You put this information into a makefile like this: Code: my_prog: my_prog.c my_prog.h gcc -o my_prog my_prog.c The first line tells make what the dependencies of my_prog are. The general form is: Code: <target>: <dependencies> As you can see, the various dependencies are listed separated by spaces. The second line tells make what command to execute if my_prog needs to be recompiled, i.e. if either (or both) of my_prog.c and my_prog.h have changed since my_prog was last compiled. As you can see, in this case the command is an invokation of the C compiler. Command lines must always begin with a tab character. This is a fairly trivial example, because we only have one source .c file. Makefiles come into their own where a project has multiple sources: Code: my_prog: my_prog_1.o my_prog2.o gcc -o my_prog my_prog_1.o my_prog_2.o my_prog_1.o: my_prog_1.c my_prog.h gcc -c my_prog_1.c my_prog_2.o: my_prog_2.c my_prog.h gcc -c my_prog_2.c Much more can be said about makefiles, but this is the basics.

12-19-2003, 12:38 PM	#8
vasudevadas Member Registered: Jul 2003 Location: Bedford, UK Distribution: Slackware 11.0, LFS 6.1 Posts: 519 Rep:	What I told you above was the absolute basics. Makefiles get much more complicated, as you are seeing. You can put macros in makefiles, these are what the dollar signs mean. A usual example is to use a macro for the command that invokes your compiler: Code: CC = gcc my_prog: my_prog.c my_prog.h $(CC) -o my_prog my_prog.c This is because the command to invoke the compiler varies from machine to machine. On Linux it is usually gcc, but on a Unix system it will probably be cc. If you use a macro for it then you only have to change it in one place - where the macro is defined - in order to make the makefile work on another system. Macros are commonly used to save typing too, like using one for the flags you pass to the compiler: Code: CC = gcc CFLAGS = -o my_prog: my_prog.c my_prog.h $(CC) $(CFLAGS) my_prog my_prog.c There's no point to it in the above example, but if you are writing a big makefile with lots of commands, and passing lots of flags to the compiler then you can see the effort saved. An at (@) symbol at the beginning of a command line means that the command being executed will not be echoed to the screen. Think of it like a "silent" option. I have no idea what circumflex (^) symbols mean, you will have to look that up in a reference somewhere. As for bits like: Code: clean: rm -f .o .-core To understand this, you need to know that you can pass arguments to the make command. Simply issuing make with no arguments causes the make utility to look for a makefile called "makefile" or "Makefile" and updates every target contained therein that requires updating. If you issue the command: Code: make <target> then make will only update the named target within the makefile. So if you have a target "clean" defined in your makefile as in the example above, issuing the command Code: make clean will cause the make utility to issue the command: Code: rm -rf .o -core i.e. remove all files in the current directory and all subdirectories that have filenames ending in .o and .core. This is a "clean up" hence the target name "clean". You will probably also see targets defined called "install" that copy executable files to places like /usr/local/bin, the effect of issuing "make install" after a "make" is thus to copy the newly compiled executables into the relevant place so that it can be accessed just like any other system command. You should notice that in these examples, the target does not actually refer to a file that gets created. It doesn't have to. Clever, eh? If you have understood all this so far then you should look for more information in various references, the O'Reilly book "Unix in a Nutshell" has a good section on the make utility. I have run out of knowledge I can give you, I hope it helped. Last edited by vasudevadas; 12-19-2003 at 12:44 PM.

12-23-2003, 03:08 PM	#12
vasudevadas Member Registered: Jul 2003 Location: Bedford, UK Distribution: Slackware 11.0, LFS 6.1 Posts: 519 Rep:	Like dolmen said, $@ is the target file, so you could say: Code: my_prog: my_prog.c my_prog.h gcc -o $@ -c my_prog.c I'm afraid I have no idea what the special macro $^ does. Type "makefile" into google and you will find a great deal of information.

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12-17-2003, 03:16 PM	#2
acid_kewpie Moderator Registered: Jun 2001 Location: UK Distribution: Gentoo, RHEL, Fedora, Centos Posts: 43,417 Rep:	a shell script is an abritrary collection of unix shell commands. put a command in a file and it is a shell script. a Makefile however is a very clever bit of scripting (in it's own language to all extents) that compiles an accompanying set of source code into a program. a spec file is typically a definition of an RPM file, what certain commands are required to run it, what it requires to work correctly and such.

12-17-2003, 05:52 PM	#3
dolmen LQ Newbie Registered: Dec 2003 Distribution: Mdk 9.2 Posts: 9 Rep:	The content of a Makefile is evaluated by the 'make' program. The content of a shell script is evaluated by the shell program (usually bash on GNU systems). What may be confusing you is that both contains call to other programs. In fact make use the shell to execute some commands in the makefile (lines that begins with a tab) based on modification time of files.

12-18-2003, 11:45 AM	#4
thomasmathew LQ Newbie Registered: Apr 2003 Location: India Distribution: Red Hat 8.0 Posts: 23 Original Poster Rep:	Thank You to everybody for there valuable reply. Now how can I write a make file. I am interested in knowing more tutorials and resources for creating error free make files. want to more details about make files. Help Me dear

12-18-2003, 05:11 PM	#5
dolmen LQ Newbie Registered: Dec 2003 Distribution: Mdk 9.2 Posts: 9 Rep:	I did a search on Google with the words "Make" and "tutorial". http://www.google.fr/search?q=Make+t...e+Google&meta= The first link seems to be what your are looking for: http://www.eng.hawaii.edu/Tutor/Make/

12-19-2003, 11:27 AM	#7
thomasmathew LQ Newbie Registered: Apr 2003 Location: India Distribution: Red Hat 8.0 Posts: 23 Original Poster Rep:	Hai Thank You for your information. But I have seen a couple of makefiles that is having some $ such as some menmonics like $^, $@ etc after the tab. I do not know how to interpret it into valid linux commands. Please give me the assistance to grasp what these lines represent. I have also seen lines like clean: rm -f .o - core These lines are so !!!! Please gimme the details of these mnemonics so as to avoid the Thank You to all the Penguin freaks for the guidance. to hear from you.

12-20-2003, 12:59 PM	#9
thomasmathew LQ Newbie Registered: Apr 2003 Location: India Distribution: Red Hat 8.0 Posts: 23 Original Poster Rep:	Thanks a lot for your interest in taking time and replying to me. I came up with writing the make files when I read the book of Linux Device Drivers - O'Reilly Publications. There is a make file written for compiling and linking two source files in the second chapter for a sample program called 'skull'. May I put the make file as written in the book. __________________________________________________________ # Change it here on specify it on the 'make' command line. KERNELDIR= /usr/src/linux include $(KERNELDIR)/.config CFLAGS= -D__KERNEL__ -DMODULE -I$(KERNELDIR)/include \ -O -Wall ifdef CONFIG_SMP CFLAGS += -D__SMP__ -DSMP endif all:skull.o skull.o: skull_init.o skull_clean.o $(LD) -r $^ -o $@ clean: rm -f .o ~ core __________________________________________________________ Can you please explain these lines to what it mean? Here you can clearly see the usage of $^ and $@ representing some mnemonics for the linking. What is the use of the including the file .config? Besides, why the SMP is defined twice like -D__SMP__ aswell as -DSMP? Is it this an OR condition for the programs that uses the __SMP__ or the SMP as the compiler control variables? Also what is the meaning of the CFLAGS option flag macro assignment line. Also .o is an object file. But what is that filed formed during compilation called the ~ core As a fact I just want to know meaning for the full lines of code above dear Please teach me!!!!! Hoping to seek a vauable reply.

12-22-2003, 05:15 PM	#10
dolmen LQ Newbie Registered: Dec 2003 Distribution: Mdk 9.2 Posts: 9 Rep:	$^ is the list of input files (skull_init.o, skull_clean.o). $@ is the target file (skull.o) The clean target is usually used to removed unneeded files. *~ are backup files created by some text editors. core is a file created by the kernel when a program crashes (which can happen during the development).

12-23-2003, 12:00 PM	#11
thomasmathew LQ Newbie Registered: Apr 2003 Location: India Distribution: Red Hat 8.0 Posts: 23 Original Poster Rep:	May I first of all express my to you all for the guidance support. Can anybody tell about more such $ mnemonics like the $^ and $@? What is the name given to this type of mnemonics in the linux jargon? Please list the set of such $ prefix in the creation of a typical makefile. with Thomas.